1. Field of the Invention
This invention relates generally to semiconductor memories. In particular, the invention relates to random access to memory chips having multi-bit outputs.
2. Description of the Related Art
In high end memory system applications, such as would be used in a large computer, one of the memory systems is the main store. The main store is typically a very large semiconductor memory system that is used to supply data and/or instructions to a cache memory. Typically, the main store is designed for block transfers of data. That is, there are multiple transfers of words constituting a block from the main store to the using system. The block transfer rate and the size of each transfer is unique to each particular application of the memory but the following comments appear to be general. The starting address of each multi-word block transfer is random with the initial fetch containing the requested memory coordinate. Once the transfer has started anywhere within the block, a wrap around is used to complete the transfer of the entire block, if necessary. A typical design for a prior art memory system is shown in FIG. 1, which a user 10 is connected to the memory through an interface 12 which provides timing, control and data buffering logic to the memory. The memory consists of N memory arrays 14, connected in parallel to the interface 12. Usually, each memory array provides one parallel bit of data. The number N of memories arrays 14 is chosen to be equal to the number of bits in an ECC (error correction) word, 72 for many large IBM computers. Thus, each bit of an ECC word is stored in and fetched from a separate memory array 14. This configuration is implemented on the IBM computers Models 3030, 3080 and 3090.
When the memory arrays 14 are relatively small, block transfers are made possible by having each memory array 14 being implemented in 16 memory chips 16, as shown in FIG. 2. Each chip 16 provides one bit to a register 18. The bits are all transferred in parallel and after the initial transfer the block transfer to the using system can begin at a random address in the register 18. The memory architecture, as shown in FIG. 3, has N memory array groups 20, each group consisting of 16 memory chips 16. The memory chips 16 are controlled over a common address and control bus 22 by address selection logic 24. Each memory array group 20 provides 16 bits in parallel to a data buffering circuit 26. When the 16 bits from each of the N memory array groups 20 have been buffered in a single transfer, the data is transferred to the using system in ECC words. As memory arrays have become denser, the point has been reached where, for total required memory capacity, the number of memory arrays is reduced below the number necessary to support the 1-bit output configuration of FIGS. 2 and 3. One approach is to use multi-bit memories, that is, memory chips with multiple parallel output lines. Examples of multiple output memory chips are disclosed by Flanagan, et al. in U.S. Pat. Nos. 4,453,237 and 4,406,013. There are further advantages, such as testing, in using multi-output memories. As described by Aichelmann, one of the present inventors, in a technical article entitled "Fault-Tolerant Design Technique for Semiconductor Memory Applications" appearing in IBM journal of Research and Development, Vol. 28, No. 2, March 1984 at pages 177-183, a single memory chip, even one having multiple outputs, should not provide more than 1 bit to an ECC word. This restriction prevents one failing chip from overwhelming the error correction capability. By default, in block transfers, the parallel bits of a multi-bit memory chip are used for different bits or words in the blocks. An example of this latter technique is described by Aichelmann in a technical article entitled "Paging From Multiple Bit Array Without Distributed Buffering", appearing in the IBM Technical Disclosure Bulletin, Volume 24, No. 1B, June 1981 at pages 485-488.
As illustrated in FIG. 4, a 4-bit memory chip 28 could transfer four bits of data at a time to a register 30. When the register 30 is filled, it contains all the bits associated with one of the N bits of the ECC word for a block transfer of 16 words. There would thus be N registers 30 in the data buffering circuit 26.
In block transfers, as previously mentioned, the requirements exist that the first word accessed be randomly addressable and that the entire block be eventually transferred. In the configuration of FIG. 4, the register 30 could be completely filled with 16 bits during four accesses to the memory chip 28 before any of those bits is randomly accessed. This approach introduces, however, an unacceptable delay in the initial access time t.sub.ACCESS.
Alternatively, the transfers from the memory chip 28 can account for the initial address of the transfer, transferring first the addressed bit to the register 30 which can then immediately be transferred to the using system. An example of the timing associated with the selective addressing and immediate serialization is illustrated in FIG. 5, for which it is assumed that bit 5 (fifth ECC word of the block of 16) is the initial address. After the select signal addresses the bits 5 through 8 and enables the memory chip 28, the four bits 5 through 8 are transferred to the register 30. As soon as this transfer is completed, bit 5 is randomly addressed in the register 30 and read out to the using system. The time for the initial access is the access time t.sub.ACCESS. Subsequently, the bits 6 through 8 are read out at a register reading rate period t.sub.N, which is considerably shorter than the access time t.sub.ACCESS.
The register reading rate period t.sub.N is considerably less than a chip reading rate period t.sub.CAS. For example, t.sub.CAS =4t.sub.N. However, while the bits are being transferred to the using system, another select signal can transfer bits 9 through 12 into the register 30. Accordingly, bit 9 is ready for serial transfer at the same reading rate period despite the disparity of the periods t.sub.n and t.sub.CAS.
Unfortunately, the above description is valid only if the initial address is aligned to a lower 4-bit boundary. In the other extreme condition, the initial address is aligned with the upper 4-bit boundary. For instance, bit 8 is addressed. In this situation, the bits 5 through 8 are transferred to the register 30. The addressing circuitry associated with the register 30 immediately outputs bit 8 to the using system, as illustrated in FIG. 6, thus maintaining the access time t.sub.ACCESS. However, because of the limitation on the chip reading rate period t.sub.CAS, bit 9, the next to be serialized, is not immediately available. Instead, a gap time t.sub.GAP develops which can be several times the register reading rate period t.sub.N, depending on what is the initial address. Needless to say, the gap time t.sub.GAP is undesirable. It could be eliminated by lengthening the access time t.sub.ACCESS to allow a second buffering transfer. However, this lengthened access time is also undesirable.